A Method of Analog IC Placement with Common Centroid Constraints

Recently most of integrated circuit chips are made from monolithic IC, which can be manufactured at low cost. In monolithic IC, absolute error which is proportion of the difference of actual value to the designed value of each element is large (several tens of percentages), but the maximum difference of the absolute error of devices on a chip, is small (a few percentages). So it is suitable to build circuits such as A/D, D/A converters and switched-capacitor filters. But if the accuracy of these circuits is required to be higher, such a small mismatch of capacitors or resistors still becomes a critical issue. The causes of the mismatch can be divided into two categories: systematic mismatch and random mismatch [1, 2]. One of the frequent systematic mismatch is caused by process gradients, whose effect can be represented by the following linear model [3]: